| Title: | verilog |
| Moderator: | ECAD2::KINZELMAN |
| Created: | Tue Mar 31 1992 |
| Last Modified: | Wed Oct 12 1994 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 21 |
| Total number of notes: | 42 |
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 13.1 | Try the Synopsys demo's. | ISEQ::COFFEY | Tue Nov 03 1992 07:07 | 9 | |
| 13.2 | Pointer | PLOUGH::KINZELMAN | Two Terms, 1 in office, 1 in jail | Tue Nov 03 1992 13:16 | 20 |
| 13.3 | SES/wb can now generate VHDL code | ECADSR::WIEDEMAN | Tue Nov 03 1992 16:32 | 10 | |
| 13.4 | ECADSR::BIRO | Mon Jan 18 1993 13:25 | 23 | ||
| 13.5 | I'll second that. | ISEQ::COFFEY | Tue Jan 19 1993 09:02 | 8 |