Conference 7.286::digital

    
    	Cool.
    
    
    	Can I get an autographed copy?
    
    		the Greyhawk

	Please consider putting all or at least some of your abstracts
on the Internet.

Thanks,

Dennis

P.S. Great idea!

RE:<<< Note 3854.2 by CX3PST::DEIMOS::D_DONOVAN "SummaNulla(The High Point of Nothing)" >>>


>	Please consider putting all or at least some of your abstracts
>on the Internet.

It is copyrighted material that Digital Press will sell. They may agree to put
the PREFACE on the Internet as a teaser, along (of course) with an order form.
The draft will be on display at US Spring DECUS next week in Washington DC in 
the Digital Press booth.

/d

    Gee,
    
    It sure would be nice to supply the material to the SALES force that is 
    responsible for selling the Alpha products, it might even be nice to
    have some copies available for us to provide to our "VITO" customers.  
    Imagine that...
    Imagine our own line people becoming more knowledgable than customers and
    channels just through reading and having access to excellent
    information in advance of release......
    Wow, just think "Whatever it Takes".....
    
    D
    
    
    
    

re Note 3854.3 by MSBCS::BHANDARKAR:

> It is copyrighted material that Digital Press will sell. 

        Of course copyrighted material may be put on the Internet
        (with the approval of the copyright holder, of course).  This
        is done all the time (in fact, Time Inc. is one of the
        publishers that puts on the Web material that they also sell
        -- not all of it, of course).

        Bob

Have you considered an excerpt in BYTE or some other such magazine ?

I saw a chapter from the book "Debugging the Development Process"
in Software Development magazine recently.  I liked it so much I
went out and bought the book - it also got nice press for Microsoft 
and Microsoft Press.

Ian Carrie

    <<< Note 3854.0 by MSBCS::BHANDARKAR "Good enough is not good enough" >>>
                          -< Upcoming book on Alpha >-

I wonder...did you go into PRISM and what the company's thinking was in 
abandoning that architecture in favor of Alpha?

I'd find that pretty interesting.

Tom

RE:                      <<< Note 3854.7 by SHRCTR::DAVIS >>>

>I wonder...did you go into PRISM and what the company's thinking was in 
>abandoning that architecture in favor of Alpha?

Yes, I do.

/d

Chapter 1 HISTORICAL PERSPECTIVE	 
 
1.1. Introduction 
1.2. Computer Performance 
1.3. The VAX Legacy 
1.4. History of RISC Developments at Digital 
1.5. The PRISM Project 
1.6. References 
 
Chapter 2 RISC DESIGN ISSUES 
 
2.1. Characteristics of Typical RISC Machines 
2.1.1 Single Cycle Issue 
2.1.2 Small number of fixed length instruction formats 
2.1.3 Load/store architecture 
2.1.4 Large number of registers	 
2.2. Typical RISC Pipeline 
2.2.1 Branch Latency 
2.2.2 Load Latency 
2.2.3 Instruction Scheduling 
2.3. Superpipelining 
2.4. Superscalar Processors 
2.5. VLIW Processors 
2.6. Advanced Implementations 
2.6.1 Out of Order Completion 
2.6.2 Out of Order Issue 
2.6.3 Register Renaming 
2.6.4 Speculative Execution 
2.7. References 
 
Chapter 3 ALPHA ARCHITECTURE	 
 
3.1. Introduction 
3.2. Alpha Architecture Design Tradeoffs 
3.2.1 Register File 
3.2.2 Multiple Instruction Issue 
3.2.3 Branch Delay Slots 
3.2.4 Suppressed Instructions 
3.2.5 Byte Load or Store Instructions 
3.2.6 Imprecise Exceptions 
3.2.7 Shared Memory Multiprocessing 
3.3. Data Representation and Processor State 
3.4. Memory Access 
3.5. Instruction Formats 
3.6. Operate Instructions 
3.6.1 Integer Arithmetic Instructions 
3.6.2 Logical Instructions 
3.6.3 Byte-manipulation Instructions 
3.6.4 Floating Point Arithmetic Instructions 
3.6.5 Miscellaneous Instructions 
3.7. Load/Store Instructions 
3.8. Branch Instructions 
3.9. PALcode 
3.9.1 PALcode for Operating System Support 
3.10. Memory Management 
3.10.1 Virtual Address Space 
3.10.2 Virtual Address Format 
3.10.3 Physical Address Space 
3.10.4 Page Table Entries 
3.10.5 Memory protection 
3.10.6 Translation Buffer 
3.10.7 Address Space Numbers 
3.10.8 Memory Management Faults 
3.11. Internal Processor Registers 
3.12. Exceptions And Interrupts 
3.13. Data Sharing 
3.14. Summary 
3.15. References 
 
Chapter 4 COMPARING RISC ARCHITECTURES 
 
4.1. Introduction 
4.2. Architectural Features 
4.3. Address Size 
4.4. Data Types 
4.5. Register sets 
4.6. Branch Model 
4.7. Instruction Sets 
4.8. MIPS Architecture Overview 
4.9. SPARC Architecture Overview 
4.10. PA-RISC Architecture Overview 
4.11. PowerPC Architecture Overview 
4.12. References 
 
Chapter 5 FIRST GENERATION ALPHA PROCESSOR CHIPS 
 
5.1. Introduction 
5.2. CMOS Process Technology 
5.3. External Interface 
5.4. Circuit Implementation 
5.5. Chip Microarchitecture 
5.6. Pipeline Organization 
5.6.1 Static and Dynamic Stages 
5.6.2 Aborts 
5.6.3 Non-Issue Conditions 
5.7. Instruction Fetch and Decode Unit 
5.7.1 Branch Prediction Logic 
5.7.2 Prefetcher 
5.7.3 Instruction Translation Buffers 
5.7.4 Interrupt Logic 
5.8. Integer Execution Unit 
5.9. Address Generation and Load/Store Unit 
5.9.1 Data Translation Buffer 
5.9.2 Bus Interface Unit 
5.9.3 Load Silos 
5.9.4 Write Buffer 
5.10. Floating Point Unit 
5.10.1 Fbox Exception Handling 
5.10.2 Fbox Exception Handling 
5.11. Performance Counters 
5.12. Cache Organization 
5.13. Scheduling and Issuing Rules 
5.13.1 Instruction Class Definition 
5.13.2 Producer-Consumer Latency 
5.13.3 Producer-Producer Latency 
5.13.4 Instruction Issue Rules 
5.13.5 Dual Issue Table 
5.14. PALcode instructions 
5.15. Memory Management 
5.16. The 21064A Microprocessor 
5.17. The 21066 Microprocessor 
5.17.1 21066 Memory Controller 
5.17.2 21066 Secondary Cache Interface 
5.17.3 Graphics Assist Functions 
5.17.4 21066 PCI Bus Interface 
5.17.5 PLL Design Issues 
5.18. 21066A Microprocessor 
5.19. Summary Comparison 
5.20. References 
 
Chapter 6 21064-BASED SYSTEM IMPLEMENTATIONS 
 
6.1. Introduction 
6.2. Digital Systems Roadmap 
6.3. High End Multiprocessor Systems 
6.3.1 System Architecture 
6.3.2 Technology 
6.3.3 System Interconnect 
6.3.4 Processor Module 
6.3.5 Memory Module 
6.3.6 I/O Subsystem 
6.3.7 System Packaging 
6.3.8 Power Subsystem 
6.4. Midrange Multiprocessor Servers 
6.4.1 System Architecture 
6.5. High Performance Workstations 
6.5.1 DEC 3000 Model 500 System Architecture 
6.5.2 CPU and Secondary Cache 
6.5.3 Memory Subsystem 
6.5.4 I/O Subsystem 
6.5.5 Clock System 
6.5.6 Technology 
6.5.7 Power and Packaging 
6.6. Entry Level TURBOchannel Workstations 
6.7. Alpha Personal Computer 
6.8. Multiprocessor Servers with PCI I/O 
6.8.1 AlphaServer 2100 
6.8.1.1 CPU Module 
6.8.1.2 Multiprocessor System Bus 
6.8.1.3 Memory Module 
6.8.2 AlphaServer 2000 System 
6.9. Workstations with PCI I/O 
6.9.1 PCI Interface Chip Set 
6.9.2 AlphaStation 200 
6.9.3 AlphaStation 400 
6.9.4 AlphaStation 250 
6.10. Low End Server with PCI I/O 
6.10.1 AlphaServer 1000 System Overview 
6.10.2 CPU Daughtercard 
6.10.3 System Motherboard 
6.10.4 Enclosure 
6.10.5 Power Supply 
6.11. CRAY T3D Massively Parallel Processor 
6.11.1 Macroarchitecture 
6.11.2 Memory Organization 
6.11.3 3-D Torus Interconnection Network 
6.11.4 Network Design 
6.11.5 Address Extension 
6.11.6 Latency-hiding Mechanisms 
6.11.6.1 Prefetch Queue 
6.11.6.2 Remote Processor Store 
6.11.6.3 Block Transfer Engine 
6.11.7 Synchronization 
6.11.8 I/O 
6.12. System Performance Summary 
6.13. References 
 
Chapter 7 SECOND GENERATION MICROPROCESSOR AND SYSTEMS 
 
7.1. Introduction 
7.2. CMOS Process Technology 
7.3. Alpha 21164 Chip Microarchitecture 
7.4. Pipeline Organization 
7.4.1 Pipeline Stages and Instruction Issue 
7.4.2 Aborts and Exceptions 
7.4.3 Non-issue Conditions 
7.5. Instruction Fetch and Decode Unit 
7.5.1 Instruction Decode and Issue 
7.5.2 Instruction Prefetch 
7.5.3 Branch Execution 
7.5.4 Instruction Translation Buffer 
7.5.5 Interrupts 
7.6. Integer Execution Unit 
7.7. Floating-Point Execution Unit 
7.7.1 Add Pipeline 
7.7.2 Multiply Pipeline 
7.7.3 Divider 
7.8. Memory Address Translation Unit 
7.8.1 Data Translation Buffer 
7.8.2 Load Instruction and the Miss Address File 
7.8.3 Store Execution 
7.8.4 Write Buffer 
7.9. Cache Control and Bus Interface Unit 
7.10. Cache Organization 
7.10.1 Data Cache 
7.10.2 Instruction Cache 
7.10.3 Second-Level Cache 
7.10.4 External Cache 
7.10.5 Cache Prefetch 
7.10.6 Serial Read-Only Memory Interface 
7.11. Scheduling and Issuing Rules 
7.11.1 Instruction Class Definition 
7.11.2 Instruction Slotting 
7.11.3 Coding Guidelines 
7.11.4 Instruction Latencies 
7.11.5 Producer-Producer Latency 
7.11.6 Issue Rules 
7.12. Replay Traps 
7.13. Miss Address File and Load-Merging Rules 
7.13.1 Merging Rules 
7.13.2 Read Requests to the Cbox 
7.13.3 Load Instructions to Noncacheable Space 
7.13.4 MAF Entries and MAF Full Conditions 
7.13.5 Fill Operation 
7.14. Mbox Store Instruction Execution 
7.15. Write Buffer and the WMB Instruction 
7.15.1 The Write Buffer 
7.15.2 The WMB Instruction 
7.15.3 Entry Pointer Queues 
7.15.4 Write-Buffer Entry Processing 
7.15.5 Ordering of Noncacheable Space Write Instructions 
7.16. Performance Counters 
7.17. PALcode 
7.18. Latency Improvements Over 21064 
7.19. High Performance Workstation 
7.19.1 System Organization 
7.19.2 System Crossbar 
7.19.3 Board Level Cache 
7.19.4 System Packaging 
7.20. Large Multiprocessor System 
7.20.1 System organization 
7.20.2 System Bus 
7.20.2.1 Memory Banks 
7.20.2.2 Address bus arbitration 
7.20.2.3 Address bus flow control 
7.20.2.4 Data bus 
7.20.2.5 Data bus arbitration 
7.20.2.6 Data bus flow control 
7.20.3 System Packaging 
7.21. References 
 
Chapter 8 PERFORMANCE CHARACTERIZATION 
 
8.1. Introduction 
8.2. Instruction Set Usage 
8.3. Cycles Per Instruction 
8.4. Operating System Activity 
8.5. Multiple Issue Statistics 
8.6. Branch  Prediction 
8.7. Cache Misses 
8.8. Translation Buffer Misses 
8.9. Stalls 
8.10. VAX and Alpha Comparison 
8.11. Pentium and Alpha Comparison 
8.12. References 
 
Chapter 9 COMPARING RISC IMPLEMENTATIONS 
 
9.1. Introduction 
9.2. RISC Microprocessor Scoreboard 
9.3. Design Styles 
9.4. Fastest RISC Microprocessors in 1995-96 
9.5. UltraSPARC 
9.6. PowerPC 620 
9.7. MIPS R10000 
9.8. PA 8000 
9.9. 21st Century 
9.10. References 
 
Chapter 10 OPERATING SYSTEMS AND COMPILERS 
 
10.1. Introduction 
10.2. Porting Openvms From VAX To Alpha 
10.2.1 Compiling VAX MACRO-32 For The Alpha Architecture 
10.2.2 Major Architectural Differences In The OpenVMS Kernel 
10.3. Porting UNIX From Mips To Alpha 
10.4. Porting Windows NT To Alpha 
10.5. Binary Translation 
10.5.1 OpenVMS VAX Translation 
10.5.2 ULTRIX MIPS Translation 
10.6. Compilers 
10.6.1 The GEM Optimizing Compiler System 
10.6.2 Code Examples 
10.6.3 Link-Time Optimization Of Address Calculation 
10.7. References 

>                             -< Complete outline >-

Gee! More than 1000 pages? Heavier than Goldenberg's VMS IDS? ;-)

RE:          <<< Note 3854.10 by OSOSPS::KAGEYAMA "Trust, but Verify" >>>
                              -< looking forward >-

>Gee! More than 1000 pages? Heavier than Goldenberg's VMS IDS? ;-)

My manuscript on 8.5"x11" paper in 10 pt font is about 250 pages. I expect that 
the typeset version will be about 350 pages. Will know when I see galley proofs
next month.

/d

    I've been wondering...
    
    what speed does, ummm, your Alpha book run at exactly? 

RE:<<< Note 3854.12 by HLDE01::VUURBOOM_R "Roelof Vuurboom @ APD, DTN 829 4066" >>>
                      -< Sorry, couldn't restrain myself >-

>    what speed does, ummm, your Alpha book run at exactly? 

It's just a paper tiger!

/d

    
    How can we internally order books from Digital Press ? and is there
    an order number on this book ?
    
    Thx

RE:                    <<< Note 3854.14 by NOTAPC::RIOPELLE >>>
                       -< Digital Press ? Book Number ? >-
    
>    How can we internally order books from Digital Press ? and is there
>    an order number on this book ?
    
It will not be available until Aug or Sep. There is no order number or price 
yet.

/d

    
    Dileep,
    
    That is quite an undertaking.  Congratulations!  Thank you for 
    entering the information about it here.  Looking forward to 
    getting a copy in the fall...and hope you will autograph it too!
    
    Cindy

re> .0                          -< Upcoming book on Alpha >-

>The book will be available in September 1995. 

Is this book available now?  If so, please tell me ISBN.

- Kazunori

"The Alpha AXP Architecture Reference Manual", Second Edition, edited by
Richard  L.Sites  and  Richard T. Witek, published by Digital Press, an
imprint of Butterworth-Heinemann, Digital part number EY-T132E-DP, ISBN
1-55558-145-5.

___Pete

The ARM 2nd Edition described in .18 is not Dileep's book described in .0

    I thought Dileep left the company.  I saw him answering some Alpha
    related questions in a usenet group but his signature indicated that he
    now works for a competetor.
    
    - Vikas

    I called Butterworth-Heinemann (1-800-366-BOOK) and ordered a copy of
    Dileep's book, even though it won't be available until Oct. 20. 
    $39.95
    
    Mark

    ... Hasn't "AXP" been nuked?
    

    re: .18 -- Dick Sites' book, Alpha AXP..., is now in the Lending
    Library.