[Search for users] [Overall Top Noters] [List of all Conferences] [Download this site]

Conference mvblab::sable

Title:SABLE SYSTEM PUBLIC DISCUSSION
Moderator:COSMIC::PETERSON
Created:Mon Jan 11 1993
Last Modified:Fri Jun 06 1997
Last Successful Update:Fri Jun 06 1997
Number of topics:2614
Total number of notes:10244

2413.0. "Can anyone explain PCI arbitration... I'm confused! :->" by RDGENG::MORRELL (You're a tiiiiiger... Roooaaaaaar.) Tue Oct 22 1996 18:06

T.RTitleUserPersonal
Name
DateLines
2413.1fixed arbitration assignmentsDANGER::PAWLOWSKIChet PawlowskiThu Oct 31 1996 17:2335
2413.2Partial-Rotating and Rotating?RDGENG::HAQUEShaheed R. Haque, 830-3531, reo2-f/b3Tue Apr 01 1997 15:427
What are the arbitration assignments when using "pci_arb=Partial-Rotating" and
"pci_arb=Rotating"? I'm specifically interested in the 2100 4/275 RM, but a
complete listing as per .1 would be nice.

[FWIW, I have a very DMA-bandwidth greedy real-time device in one of the PCI
slots and when I do some SNMP stuff, using the built in tu0, it seems to get
starved of bandwidth].
2413.3A pointer would do!RDGENG::HAQUEShaheed R. Haque, 830-3531, reo2-f/b3Thu Apr 03 1997 07:357
>What are the arbitration assignments when using "pci_arb=Partial-Rotating" and
>"pci_arb=Rotating"? I'm specifically interested in the 2100 4/275 RM

Is there a technical manual, or even module functional spec. that contains
this information?

	Thanks, Shaheed
2413.4partial and rotating info.MAY21::SAVAGEWed Apr 09 1997 22:3380
    			DIGITAL INTERNAL ONLY
    
    Attached below is mail I sent to Shaheed on the pci arb assignments for
    partial rotating and rotating.  For simplicity in explaining the scheme
    - the assumption is made all signals were asserted.  Thanks to Chet on
    help with this info.
    	-Phyllis

Hi Shaheed,
  With help from Chet I've gathered the PCI Arb. info. you requested on
rotating and partial rotating for the 2x00 product.  If you need further 
info. or clarification let me know.
	-Phyllis

If you assume everything was asserted then the priority scheme for rotating
would be as listed below.  This would hold true for partial rotating as well.
However, under partial rotation several of the lines/signals get a "boost"
(the term Chet uses and as I undertstand it essentially a higher priority) over
another.  So for example, using the 2100, if both the EISA bridge and PCI
Option Slot 0 were asserted then the EISA bridge would be selected.  If the
CPU (loads and stores to/from PCI or EISA) and local Ethernet controller both
asserted at the same time then CPU (loads and stores to/from PCI or EISA) would
be selected.  I've listed this "boost" info. for each system; this holds true
for partial rotating.

================================================================================
Rotating
    For the 2100
    	1)	EISA bridge
    	2)	PCI Option Slot 1
    	3)	CPU (loads and stores to/from PCI or EISA)
    	4)	PCI Option Slot 0
    	5)	PCI Option Slot 2, shared with local SCSI controller
    	6)	local Ethernet controller

Uner partial rotating 
	- EISA bridge would get a "boost" over PCI Option Slot 0
	- CPU (loads and stores to/from PCI or EISA) would get a "boost" over
	  local Ethernet controller
================================================================================
    For the 2000

    	1)	EISA bridge
    	2)	PCI Option Slot 1
    	3)	CPU (loads and stores to/from PCI or EISA)
    	4)	PCI Option Slot 0
    	5)	local SCSI controller
    	6)	PCI Option Slot 2

Uner partial rotating 
	- EISA bridge would get a "boost" over PCI Option Slot 0
	- CPU (loads and stores to/from PCI or EISA) would get a "boost" over
	  PCI Option Slot 2
================================================================================
    For the 2100A
    
    	1)	EISA bridge
    	2)	PCI Option Slot 7
    	3)	CPU (loads and stores to/from PCI or EISA)
    	4)	PCI Option Slot 4, shared with PCI Option Slot 6
    	5)	PCI Option Slot 5
    	6)	PCI Option Slots 0-3 (behind the PCI-PCI bridge)

Uner partial rotating 
	- EISA bridge would get a "boost" over PCI Option Slot 4, shared
	  with PCI Option Slot 6
	- CPU (loads and stores to/from PCI or EISA) would get a "boost"
	over PCI Option Slots 0-3 (behind the PCI-PCI bridge)


                                 
Chet noted in his reply to the 2413 note the rackmount differs in how 
the slots are numbered: slots 0-2 being the reverse of the pedestal.

Also mentioned in several notes files entries: if you have a REV. A2 PCEB and 
console version 4.3 or greater, the arbitration will remain at fixed.  You
can determine the rev. via the examine command at the console prompt:
		P00>>>e -b econfig:20008
A value of 03 is an A2 rev.; greater than 03 will be a B0 or greater rev.
    
2413.5Thanks, Phyllis!RDGENG::HAQUEShaheed R. Haque, 830-3531, reo2-f/b3Mon Apr 14 1997 13:2476
After a follow-up question, Phyllis confirmed that in her descriptions, "1)" is
higher priority than "6)".

She also provided the following information clarifying the exact meaning of the
term "boost" as applied to the partial-rotating scheme.

================================================================================

For the "boost" info. - Using the conceptual diagram below (borrowed from the
INTEL chip spec.) and using input for the AS2100 as an example may help explain
the partial rotating scheme.

  The arbiter consists of four banks that can be configured so that the six
masters can be arranged in the various priority schemes.  As mentioned in
Sable note 1543.9 the AS2100 need 7 inputs so a fair round robin scheme
was setup for two of those lines so two input are listed together.

 Looking at bank2: if all lines were asserted then pure rotation would be 
bank0 followed by bank3 followed by bank1 and then all over again ->bank0, 
bank3, bank1.  So the first time around within bank0 the EISA bridge would
get selected; within bank3 the CPU etc. would be selected, within bank1 PCI
slot2 etc. next time around for bank0 now PCI Option slot 1 would get selected;
bank3 PCI Option slot 0 and bank1 Ethernet.  

  For partial rotation however there is this "boost" factor.  The rotation
would still be bank0 followed by bank3 and then bank1.   However, depending
upon what signals are asserted, within bank0 and also within bank1, will bring
into play this partial rotating scheme, it is no longer purely rotating.
Should the EISA Bridge be asserted, the next time around for bank0 it will be
selected over the PCI Pption slot 1 line.  Similarly for bank1 - PCI Option
slot2 etc., if asserted, will be selected over the ethernet line.  Restated it
says each time through bank0 if the EISA line is asserted it will be selected
and for bank1 if the CPU etc. line is asserted it will be selected.  You should
be able to extrapolate this info. for both the AS2000 and AS2100A from the list
in my previous mail.

  The F0, F3, F1 represent the fixed control line for that bank 0, 3 or 1.
Simlarly R0, R3 and R1 represent the rotate control for that bank 0, 3, or 1
I can only guess at the specific represetation for the 0 and 1.


****AS2100****
			  F0  R0
			  |   |
			+-+---+-+
			|	|
EISA Bridge ------------|0	|
			|	|
			|Bank 0	|---+---+
			|	|	|
PCI Option -------------|1	|	|
Slot 1			|	|	|
			+-------+	|
			  F3  R3	|
			  |   |		|
			+-+---+-+	|	+---------------+
			|	|	+-------|00		|	
CPU (loads and stores --|0	|		|		|
to/from PCI or EISA)	|	|		|		|
			|Bank 3	|---------------|01 Bank 2	|
			|	|		|		|
PCI Option ------------	|1	|		|		|
Slot 0			|	|	+-------|10		|
			+-------+	|	+-+-+-------+---+
					|	  | |	    |
			  F1  R1	|        Fixed    Rotate
			  |   |		|       control   control
			+-+---+-+	|	bank 2	  bank 2
			|	|	|
PCI Option slot 2, -----|0	|	|
shared with local 	|	|	|
SCSI controller		|Bank 1	|---+---+
			|	|
local Ethernet ---------|1	|
controller		|	|
			+-------+