| T.R | Title | User | Personal
Name | Date | Lines |
|---|
| 24.1 | My vote goes to VHDL | ESASE::BMURPHY | Brendan Murphy Galway | Wed Jan 20 1988 08:10 | 22 |
| 24.2 | Sounds worth looking at! | CETI::HAQUE | | Mon Jan 25 1988 15:07 | 19 |
| 24.3 | Documentation, please. | DECSIM::GIRAMMA | Your development dollars at work. | Tue Jan 26 1988 11:53 | 11 |
| 24.4 | Some VHDL references... | GNERIC::SMITH | Michael J. Smith, MLO 21-4 | Wed Jan 27 1988 10:40 | 35 |
| 24.5 | IEEE Standard VHDL 1076 References | JANUS::PARASKEVA | Mark | Wed Jan 27 1988 15:07 | 79 |
| 24.6 | Reply to 24.3: Don't leap to Ada | JANUS::PARASKEVA | Mark | Wed Jan 27 1988 15:21 | 17 |
| 24.7 | VHDL 1076 Features | JANUS::PARASKEVA | Mark | Thu Jan 28 1988 08:48 | 133 |
| 24.8 | A few naive questions on VHDL | DECSIM::HEILMAN | Get 'em out by Friday | Thu Jan 28 1988 12:43 | 20 |
| 24.9 | Reply to 24.8 | JANUS::PARASKEVA | Mark | Thu Jan 28 1988 22:20 | 78 |
| 24.10 | VHDL allows high-level STRUCTURAL models | CADSYS::SCHUMANN | | Fri Jan 29 1988 19:49 | 12 |
| 24.11 | Just a small matter of programming? | DECSIM::GROSS | David Gross | Mon Feb 01 1988 17:02 | 8 |
| 24.12 | low-level model implementation | CADSYS::SCHUMANN | | Tue Feb 02 1988 13:20 | 10 |
| 24.13 | In reply to 24.11: built-in functions | JANUS::PARASKEVA | Mark | Wed Feb 03 1988 12:56 | 12 |
| 24.14 | that's not a bug, that's a feature! | CADSYS::INSINGA | Aron K. Insinga | Wed Feb 03 1988 15:49 | 24 |
| 24.15 | reply to 24.14: high level VHDL structural models | JANUS::PARASKEVA | Mark | Thu Feb 04 1988 08:45 | 39 |
| 24.16 | Clarification | CADSYS::SCHUMANN | | Thu Feb 04 1988 14:04 | 32 |
| 24.17 | VHDL Signal Assignment Statements | JANUS::PARASKEVA | Mark | Thu Feb 04 1988 17:51 | 53 |
| 24.18 | Can you transport VHDL models? | DECSIM::GROSS | David Gross | Fri Feb 05 1988 15:06 | 15 |
| 24.19 | reply to 24.18: foreign subprograms | JANUS::PARASKEVA | Mark | Mon Feb 08 1988 08:01 | 18 |
| 24.20 | DECSIM is, after all, extremely flexible! | CADSYS::INSINGA | Aron K. Insinga | Tue Feb 09 1988 16:50 | 19 |
| 24.21 | VHDL <--> BDS is not so direct as claimed | PASTA::WATERS | | Tue Feb 09 1988 17:39 | 71 |
| 24.22 | 20x difference | CADSYS::SCHUMANN | | Tue Feb 09 1988 19:11 | 76 |
| 24.23 | Are the SIM90 team looking? | JANUS::PARASKEVA | Mark | Wed Feb 10 1988 07:02 | 13 |
| 24.24 | Yes, indeed, the Sim90 Team is Looking! | CAD::SAKALLAH | Karem | Wed Feb 10 1988 12:43 | 12 |
| 24.25 | Create VHDL Models NOW with BDS and Ada! | JANUS::PARASKEVA | Mark | Fri Mar 11 1988 08:06 | 113 |
| 24.26 | please let us know what's happening | CADSYS::SCHUMANN | | Thu Mar 31 1988 12:38 | 20 |
| 24.27 | Sudhir Kadkade and Thomas Lowell progressing... | DECSIM::ALDRIDGE | | Fri Apr 01 1988 12:49 | 25 |
| 24.28 | need basic information | CADSYS::SCHUMANN | | Tue Apr 05 1988 13:59 | 25 |
| 24.29 | Understand and Document the problem space first... | DECSIM::ALDRIDGE | | Wed Apr 06 1988 15:36 | 31 |
| 24.30 | HDL sub-team aims are UNCLEAR | JANUS::PARASKEVA | Mark | Thu Apr 07 1988 19:34 | 54 |
| 24.31 | Come-on now | DECSIM::GROSS | David Gross | Fri Apr 08 1988 14:26 | 56 |
| 24.32 | n HDL's is (n-1) too many | CADSYS::SCHUMANN | | Fri Apr 08 1988 15:46 | 10 |
| 24.33 | Valid Issue: multiple HDL's ??? | DECSIM::ALDRIDGE | | Sat Apr 09 1988 13:24 | 17 |
| 24.34 | Please only one HDL - VHDL | COMAE::COLLIS | Steve | Mon Apr 11 1988 13:41 | 62 |
| 24.35 | Still waiting for clarification | JANUS::PARASKEVA | Mark | Mon Apr 11 1988 14:56 | 10 |
| 24.36 | Historical note | DECSIM::GROSS | David Gross | Mon Apr 11 1988 17:26 | 4 |
| 24.37 | The HDLs need not be distinct | DECSIM::GROSS | David Gross | Mon Apr 11 1988 18:42 | 46 |
| 24.38 | sounds like a problem of perspective | PASTA::WATERS | | Mon Apr 11 1988 22:47 | 14 |
| 24.39 | Some Questions? | JANUS::PARASKEVA | Mark | Tue Apr 12 1988 13:05 | 85 |
| 24.40 | I hope I am a bit clearer this time | DECSIM::GROSS | David Gross | Tue Apr 12 1988 21:11 | 217 |
| 24.41 | Announcing the VHDL Conference | JANUS::PARASKEVA | Mark | Tue Apr 12 1988 23:38 | 18 |
| 24.42 | Some points! | JANUS::PARASKEVA | Mark | Wed Apr 13 1988 09:59 | 216 |
| 24.43 | let's not jump to conclusions | AITG::INSINGA | Aron K. Insinga | Mon Apr 18 1988 02:01 | 41 |
| 24.44 | One company, one input syntax | JANUS::HAQUE | Shaheed R. Haque, 830-3531, reo2-g/m2 | Mon Apr 25 1988 10:46 | 29 |
| 24.45 | first stage results? | CADSYS::SCHUMANN | | Wed May 11 1988 13:10 | 14 |
| 24.46 | In search of the ultimate HDL | JANUS::PARASKEVA | Mark | Thu May 19 1988 23:00 | 5 |
| 24.47 | declarative HDL | IOENG::JWILLIAMS | Zeitgeist Zoology | Thu Jun 02 1988 19:14 | 26 |
| 24.48 | has SIM90 been cancelled? | STRSHP::SCHUMANN | | Fri Jun 03 1988 14:00 | 6 |
| 24.49 | No Prologs please | DECSIM::GROSS | David Gross | Fri Jun 03 1988 16:39 | 9 |
| 24.50 | patience, patience | DECSIM::FARMER | | Wed Jun 08 1988 20:11 | 13 |
| 24.51 | A question of logic | IOENG::JWILLIAMS | Zeitgeist Zoology | Mon Jun 20 1988 19:02 | 56 |
| 24.52 | SIM90 will accept VHDL | DECSIM::ALDRIDGE | | Tue Jul 19 1988 20:54 | 25 |
| 24.53 | did anyone capture MCC's VHDL test suite | PASTA::WATERS | | Wed Jul 27 1988 14:10 | 8 |
| 24.54 | Verilog hear-say | PASTA::WATERS | | Fri Aug 05 1988 13:37 | 20 |
| 24.55 | Wrong order of VHDL and Ada in 24.36 | GSPMO::WALLACE | | Wed Oct 19 1988 22:44 | 8 |
| 24.56 | VHDL Seminar? | NUPE::HAMPTON | ...and the world will be as one. | Thu Aug 24 1989 19:47 | 11 |
| 24.57 | Try Ray, he really knows this stuff | DECSIM::GROSS | The bug stops here | Fri Aug 25 1989 16:30 | 4 |
| 24.58 | see VHDL notes file (23.0) for course details | BOOTIS::PARASKEVA | Mark . . RE02/GD3 830-4020 | Fri Sep 01 1989 21:22 | 0
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