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1. Yes. The Dranetz 606 can detect the 16-20 ms.
2. This question is not so easily answered. Basically at 50-Hz, the
drop-out is about 20-ms. Older systems will likely fail. Our newer
ones should not. See EL00122-00, page 20. Find this through SMC on
VTX or at http://www-server.mso.dec.com/elclass/dec_stds.htm. Specific
methods for measurement are given in EL00122-01.
In Figure 5: (not shown here - refer to EL00122-00)
t1 is ride-through time. It represents the time required to sense ac
power loss and to provide an output signal to initiate power down
routine. This ride-through time may be any number greater than 0. The
shorter this time is made however, the greater the frequency of
nuisance shutdowns will occur due to short power line disturbances and
noise. This time should be made as long as possible consistent with
other product and system requirements and trade-offs of size and cost.
t2 represents the duration required to guarantee orderly power-down of
computer operation. This duration is determined by product and system
requirements. A typical value might be 5 ms to store all volatile
registers away in nonvolatile memory.
t3 represents the duration of valid power remaining following the
completion of t2. This time may be any duration equal to or greater
than 0.
t1 + t2 + t3 = hold-up time
New power supply designs that must interface with existing power fail
detect circuitry must provide sufficient hold-up capacity to be
consistent with the specific power fail detect circuit specifications.
NOTE
Typically 20 ms hold-up time duration is required.
New power supply designs incorporating their own power fail detect
circuitry must provide sufficient hold-up capacity to be compatible
with the detect circuitry and with the appropriate system specification
in which they will be used.
It really depends on how loaded the power supplies are and how large the
regulator capacitance is for the dc-buss. Truly, the system does
not care what happens to the AC input, so long as the dc-buss remains
valid. But the system has only milli-seconds to save context on a
power fail, so the entire process starts when the AC power falls below
a critical value and stays there for a certain time, t1 above, perhaps
5-8 ms. While power is VALID, the power-down routine runs and when
complete, POWER_VALID is de-asserted, t2 above. Then the dc-buss is
dropped, t3 period above. What will happen if the AC power is
re-asserted and AC_LOW is de-asserted during this process?? That will
depend, I think, upon the firmware control routines within the machine.
Batteries are used in some systems to sustain the dc-buss for
longer periods and power control routines (firmware) in the system can
enhance this operation.
Do the Sun and HP use battery backup?? Do our systems in this
particular instance??
"If a power system loses 1 cycle of power, can we consider it is
acceptable?" Are you asking for a specification for a specific system?
Or is your question more general? Each system has a tolerance, but
generally all of our systems will run with 8-10 ms outage, regardless
of age or style and newer ones should run for about 20-ms.
You can find TMs for almost all of our newer systems on TICAP using
browser (Netscape or Internet Explorer) at http://neacs4.das.dec.com/
The TM for your specific system may provide some further information.
If you cannot find some information which helps you, please contact the
EEC at CSCMA::DSN%EEC and we will find an answer for your specific
question
I've sent a separate message to you with some contact info and further
information.
JR Moore
EEC Support
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