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In normal circumstances, with fixed speed clocks, it only matters
to find a stable part of the clock to trigger off. A common trick
is to use inverted clocks to sample one half bit late in order to
get a stable part of the data signal.
With variable speed clocks late sampling is a disaster because if
it works at 6M, it will be exactly wrong at 3M (because half a bit
is now a bit time).
Hence you must use short cable lengths and reflected clocks at 6M.
Apart from really making sure that it is a 622HS card - see if it
can measure the clock speed accurately - don't trust the label - all
the other problems we have had have been down to Digital Link.
1) they don't support reflected clocks properly (eg DECNIS if
DECNIS reports an unrealistic clock speed).
2) they get confused if the T1's timing isn't synchronised (eg a
mixture of old analogue and new digital circuits).
Peter
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