| Re: .14
> I've seen lots of warnings concerning the reliable use of 150ns
> memory on Amigas.
There was a fellow who claimed that 150ns chips were too slow on USENET.
However, unless you have a poorly designed board, 150ns chips should
work just fine.
Personally, when I had a 1000 and a Starboard, I used 150ns chips
without any trouble for over a year (until I upgraded to a 2000).
What follows is the discussion that appeared on USENET after the
initial "150ns is too slow" posting. By the way, Dave Haynie
is the designer of the Amiga 500, the B2000, the Commodore 68020
card, and the Commodore 68030 card.
<<< FRAIS2::FRAIS2$DUA0:[NOTES$LIBRARY]AMIGA_SYS.NOTE;1 >>>
-< comp.sys.amiga - postings >-
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Note 2108.0 Fix that baby! (RAM Board clarifications) 4 replies
FRAIS2::ZIMMERMANN "cbmvax!daveh" 58 lines 22-SEP-1989 05:35
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From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.amiga
Subject: Re: Fix that baby! (RAM Board clarifications)
Message-ID: <7966@cbmvax.UUCP>
Date: 21 Sep 89 18:45:09 GMT
References: <1982.AA1982@americ>
Distribution: na
Organization: Commodore Technology, West Chester, PA
Lines: 47
in article <1982.AA1982@americ>, erk@americ.UUCP (Erick Parsons) says:
> This can be especially prominent with fast expansion devices like hard
> drives and frame grabbers. Number one on the list of bad boards are all
> those RAM boards with 150 nano-second RAMs. This is the time it takes the
> RAM to access valid data. The smaller this number the better.
You're confused. While it's true that the rating of the DRAM device, such
as 150ns, indicates one aspect of the device's access time, that's hardly
an indication of performance. It's certainly possibly to build a perfectly
acceptible, full speed Amiga memory board with 150ns parts. A 150ns device
has a cycle time of 270ns or better. The _minimum_ memory cycle time on
the Amiga bus is 560ns. Clearly, some margin exists for a good design using
150ns parts. In fact, the CHIP memory in your system is very likely 150ns
DRAM, and it's actually running 280ns cycles (interleaved Agnus and 68000
accesses).
Now it's also a fact that, with a bad memory board design, even 80ns parts
aren't going to help you out much. If you put 80ns chips into any A2000
style memory board you're wasting money. In general, if you use any part
that's rated faster than a board calls for, you're wasting money -- the
part's speed is only a potential speed. The actual speed of operation is
limited by [a] the Amiga system, which sets the minimum cycle time of 560ns,
and [b] the memory board design, which could impose wait states, depending
on it's design.
Most of the memory boards out there, like A2052 or A2058, ASDG, MicroBotics'
8-Up, etc. run at the full bus speed with generally hidden refesh cycles.
Even if a memory board does add wait states, all that's going to do is slow
you down, it's not going to make anything unreliable. And in most cases,
changing to faster DRAM isn't going to help; the memory timing is set by the
board design.
The only case in which changing to a faster memory device will help is if you
have a memory board that, for some reason, is populated with parts that are
too slow for it's design. Certainly the reputable manufacturers don't ship
memory boards with incorrect parts, and they also don't recommend the wrong
parts for boards that are shipped unpopulated. So unless you're experiencing
flakey operation with a memory board from some fly-by-night operation, or
on something you hacked together in your cellar, you're not likely to gain
anything, except space in your wallet, by going to a faster set of DRAMs.
> Erick Parsons // Knowledge is little more than knowing the questions
--
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
{uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy
Too much of everything is just enough
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Note 2108.1 Fix that baby! (RAM Board clarifications) 1 of 4
FRAIS2::ZIMMERMANN "hub!dougp" 30 lines 23-SEP-1989 03:23
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From: dougp@voodoo.ucsb.edu
Newsgroups: comp.sys.amiga
Subject: Re: Fix that baby! (RAM Board clarifications)
Message-ID: <2367@hub.UUCP>
Date: 22 Sep 89 02:52:06 GMT
Sender: news@hub.UUCP
Distribution: na
Organization: UC, Santa Barbara. Physics Computer Services
Lines: 19
-Message-Text-Follows-
In article <7966@cbmvax.UUCP>, daveh@cbmvax.UUCP (Dave Haynie) writes...
>has a cycle time of 270ns or better. The _minimum_ memory cycle time on
>the Amiga bus is 560ns. Clearly, some margin exists for a good design using
^^^^^ Is this always true? My understanding is that
the 68000 only needs to access ram every other cycle which would
explain the timing (well almost, 1/7.14Mhz = 140ns, *2=280ns).
But other devices hanging on the bus, say a hard disk with DMA, or
even the 2620 might be able to access the bus every cycle.
Perhaps you could help with a simplified discription of what
determines the bus timing especialy where that factor of 2 and 4
comes from
>Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
> {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy
Douglas Peale
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Note 2108.2 Fix that baby! (RAM Board clarifications) 2 of 4
FRAIS2::ZIMMERMANN "auc!rar" 45 lines 23-SEP-1989 04:48
-< A 68000 bus cycle is four cpu clock cycles, isn't it? >-
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From: rar@auc.UUCP (Rodney Ricks)
Newsgroups: comp.sys.amiga
Subject: Re: Fix that baby! (RAM Board clarifications)
Summary: A 68000 bus cycle is four cpu clock cycles, isn't it?
Keywords: memory bus
Message-ID: <32285@auc.UUCP>
Date: 22 Sep 89 13:53:47 GMT
References: <2367@hub.UUCP>
Reply-To: rar@auc.UUCP (Rodney Ricks)
Distribution: na
Organization: Atlanta University Center, Atlanta, Ga.
Lines: 31
In article <2367@hub.UUCP> dougp@voodoo.ucsb.edu writes:
>-Message-Text-Follows-
>In article <7966@cbmvax.UUCP>, daveh@cbmvax.UUCP (Dave Haynie) writes...
>>has a cycle time of 270ns or better. The _minimum_ memory cycle time on
>>the Amiga bus is 560ns. Clearly, some margin exists for a good design using
> ^^^^^ Is this always true? My understanding is that
>the 68000 only needs to access ram every other cycle which would
>explain the timing (well almost, 1/7.14Mhz = 140ns, *2=280ns).
I'm no hardware expert, but from my understanding, doesn't the 68000 have
four CPU clock cycles for every memory bus cycle? If so, that would change
your timing calculation to be...
1 / 7.14 Mhz = 140ns, 140ns * 4 = 560ns
>But other devices hanging on the bus, say a hard disk with DMA, or
>even the 2620 might be able to access the bus every cycle.
Maybe the bus was designed to run only as fast as the 7.14 Mhz 68000
can access it.
>>Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
>> {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy
>
>Douglas Peale
--
"We may have come over here in different ships,
but we're all in the same boat now." -- Jesse Jackson
Rodney Ricks, Morehouse Software Group
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Note 2108.3 Fix that baby! (RAM Board clarifications) 3 of 4
FRAIS2::ZIMMERMANN "arrakis.nevada.edu!maniac" 39 lines 23-SEP-1989 05:51
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From: maniac@arrakis.nevada.edu (ERIC SCHWERTFEGER)
Newsgroups: comp.sys.amiga
Subject: Re: Fix that baby! (RAM Board clarifications)
Keywords: memory bus
Message-ID: <840@unsvax.NEVADA.EDU>
Date: 22 Sep 89 18:46:37 GMT
References: <2367@hub.UUCP> <32285@auc.UUCP>
Sender: news@unsvax.NEVADA.EDU
Reply-To: maniac@arrakis.nevada.edu.uucp (ERIC SCHWERTFEGER)
Distribution: na
Organization: Univ of Nevada System Computing Services - Las Vegas
Lines: 25
Having done designs for a 68000 based single board computer with
DRAM memory (years ago), I can add to this discussion on what speed memory
is needed on the amiga,
While it is true that the memory cycle on the amiga (for the cpu)
is 560 ns, the CPU doesn't give the memory that much time to read. First
of all, the address isn't made available until half way through the
first clock cycle, and doesn't say that that is a valid address until
the end of the first clock cycle (you can, however work around this).
Now, the data is expected in by the start of the fourth clock cycle. This
gives the memory 2 clock cycles, or 280 ns to respond. Now, you can figure
on another 100 ns of overhead for memory decoding, buffering, etc. Remember
that light only travels less than a foot in 1 ns, and those paths through
the chips are hardly straight, or at full speed. The overhead gets even
worse when you have to deal with an expandable system like the Amiga.
Now that all that is done, you have about 180 ns for a memory
access, unless the memory board is poorly designed or some other design
consideration took precidence. In the Ram board I have (EXP -1000),
I have a mix of 150 ns and 120 ns memory, and unless I pull all my
150 ns chips, I need to let my Amiga warm up for a few minutes in order
to boot. I have heard of one memory expansion/hard disk unit (can't remember
the name), that requires 80 ns rams, due to higher overhead.
Hope this information helps.
Eric Schwertfeger, UNLV, maniac@arakis.nevada.edu
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Note 2108.4 Fix that baby! (RAM Board clarifications) 4 of 4
FRAIS2::ZIMMERMANN "cbmvax!daveh" 64 lines 26-SEP-1989 05:06
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From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.sys.amiga
Subject: Re: Fix that baby! (RAM Board clarifications)
Message-ID: <7988@cbmvax.UUCP>
Date: 25 Sep 89 16:28:38 GMT
References: <840@unsvax.NEVADA.EDU>
Distribution: na
Organization: Commodore Technology, West Chester, PA
Lines: 53
in article <840@unsvax.NEVADA.EDU>, maniac@arrakis.nevada.edu (ERIC SCHWERTFEGER) says:
> Keywords: memory bus
> While it is true that the memory cycle on the amiga (for the cpu)
> is 560 ns, the CPU doesn't give the memory that much time to read.
True -- it looks like this:
+------------Cycle Time = 560ns---------+
| |
s0 s1 s2 s3 s4 s5 s6 s7
+----+ +----+ +----+ +----+ +---
| | | | | | | | |
7M -+ +----+ +----+ +----+ +----+
| |
+-------280ns-------+
Access Time
> Now, the data is expected in by the start of the fourth clock cycle. This
> gives the memory 2 clock cycles, or 280 ns to respond.
But, we are talking only _access_ time for memory, too, not just the 68000.
Both have cycle times, both have access times.
> Now, you can figure on another 100 ns of overhead for memory decoding,
> buffering, etc.
If you have 4 levels of buffering between the 68000 and the board (as with
autoconfigured boards), you might get at worst 50ns of delay. It's not
even as bad as all that. If you're building a DRAM board, you _could_
assert RAS* as soon as AS* falls, even before you're certain of SLAVE*
being valid. Give the DRAMs 180ns from RAS* (room for buffer delays and
slop), and you're left with over 70ns from the time AS* is valid on your
board before RAS* need be asserted. That, my friend, is FOREVER.
> In the Ram board I have (EXP -1000), I have a mix of 150 ns and 120 ns
> memory, and unless I pull all my 150 ns chips, I need to let my Amiga
> warm up for a few minutes in order to boot.
Like I've said before, it's up to the designer to insure his/her design
will work with any specific speed part. You can certainly simplify your
design in many cases by requiring a faster part. I'm sure you don't have
to pull the 150ns DRAM from your Amiga's motherboard to power up :-).
>
> Eric Schwertfeger, UNLV, maniac@arakis.nevada.edu
--
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
{uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy
Too much of everything is just enough
|