| Title: | -={ H A C K E R S }=- |
| Notice: | Write locked - see NOTED::HACKERS |
| Moderator: | DIEHRD::MORRIS |
| Created: | Thu Feb 20 1986 |
| Last Modified: | Mon Aug 03 1992 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 680 |
| Total number of notes: | 5456 |
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 647.1 | here's some resuls from UMLIT (re.0) | DECSIM::FARMER | Sun Jan 03 1988 20:27 | 46 | |
Times for selected instructions on recent architectures
uVAX 780 8200 8600 8800 (cy) avge
MOVL Reg,Reg 0.44 0.40 0.40 0.10 0.09 (2) .29
ADDL2 Reg,Reg 0.44 0.40 0.39 0.10 0.14 (3) .29
CLRL Reg 0.66 0.60 0.60 0.08 0.09 (2) .41
ADDL3 Reg,Reg,Reg 0.69 0.60 0.81 0.16 0.21 (5) .49
CLRQ Reg 0.88 1.20 0.80 0.16 0.14 (3) .64
BRW 1.17 0.85 0.73 0.29 0.25 (6) .66
MOVL Mem,Reg 1.32 0.85 0.81 0.30 0.15 (3) .69
MOVL Reg,Mem 1.27 1.25 0.95 0.30 0.14 (3) .78
TSTL + BLEQ 1.40 1.01 1.01 0.40 0.32 (7) .83
CMPL + BLEQ 1.56 1.23 1.19 0.44 0.40 (9) .96
BBS #22,Reg,disp 1.33 1.40 1.61 0.56 0.39 (9) 1.06
ADDF2 Reg,Reg 2.96 0.79 1.46 0.24 0.32 (7) 1.15
ADDF3 Reg,Reg,Reg 2.94 1.20 1.91 0.32 0.36 (8) 1.35
BBCC #22,Reg,disp 1.95 1.60 2.31 0.80 0.45 (10) 1.42
MOVL Mem,Mem 2.83 1.75 2.11 0.56 0.25 (6) 1.50
MULF2 Reg,Reg 3.89 1.21 2.03 0.32 0.45 (11) 1.58
ASHL #10,Reg,Reg 2.03 2.01 5.49 0.56 0.54 (12) 2.13
JSB + RSB 3.61 3.01 2.93 1.27 0.73 (16) 2.31
CMPV #2,#7,Reg,#-2 3.14 2.82 4.83 0.48 0.59 (13) 2.37
EXTZV #4,#10,Reg,Reg 3.83 2.61 4.84 0.88 0.57 (13) 2.55
EXTV #4,#10,Reg,Reg 3.65 3.02 5.65 0.88 0.54 (12) 2.75
MULL2 Reg,Reg 5.24 1.86 5.92 0.64 0.75 (17) 2.88
CMPZV #2,#7,Reg,#-2 4.64 3.02 5.37 0.88 0.62 (14) 2.91
DIVF3 Reg,Reg,Reg 4.71 4.69 2.76 1.38 1.61 (36) 3.03
INSV Reg,#4,#10,Reg 5.17 3.42 5.79 1.20 0.63 (14) 3.24
EMUL Reg,Reg,Reg,Reg 6.40 6.93 3.48 0.73 0.95 (21) 3.70
DIVL2 Reg,Reg 8.47 9.47 8.23 1.71 2.07 (46) 5.99
DIVL3 Reg,Reg,Reg 8.69 9.67 7.67 2.57 2.12 (47) 6.14
INSQUE + REMQUE 10.70 13.94 8.76 2.41 1.92 (43) 7.55
EDIV Reg,Reg,Reg,Reg 11.43 11.88 7.47 4.01 3.34 (74) 7.63
CALLG #0,Rtn + RET, 0 GPRs 12.85 13.65 12.79 3.02 1.49 (33) 8.76
CALLS #0,Rtn + RET, 0 GPRs 14.10 14.33 14.20 3.42 1.66 (37) 9.54
CALLS #0,Rtn + RET, 5 GPRs 21.33 23.56 17.51 4.60 2.76 (61) 13.95
INSQHI + REMQHI 19.48 27.38 25.01 5.09 10.08 (224) 17.41
CALLS #0,Rtn + RET, 10 GPRs 27.23 32.22 25.49 5.64 3.34 (74) 18.78
CMPC3 Reg,(Reg),(Reg), 10 chr 83.41 14.30 10.30 3.85 2.71 (60) 22.91
MOVC5 #0,(R1),#0,#512,BLOCK 124.58 111.66 63.20 13.17 11.14 (247) 64.75
1. instruction times are average/typical, in micro-seconds.
2. numbers in parentheses are 8800 cycles, which, if not
exact, are meant as a relative comparison to the instructions.
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| 647.2 | ERIS::CALLAS | I've lost my faith in nihilism. | Mon Jan 04 1988 19:08 | 10 | |
I find seeing the 780, the 8200, and the 8600 in a list of "recent
architectures" to be amusing. Not only are they more correctly
different implementations of a single architecture, the VAX
archtecture, but it is amusing to see the 780 called "recent." I'm not
criticizing your putting it there -- it's nice to see it as a reference
point, but would be nicer to see timings for the "turbo" versions of
the 8200 and 8600 -- the 8250 (even better if you find one with a
working M-chip) and 8650, as these are more common.
Jon
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| 647.3 | DECSIM::FARMER | Mon Jan 04 1988 21:17 | 6 | ||
I did put the 780 times as a reference point for the other "implementations". I only got times for the "implementations" I have access to. I can send the procedure to anyone who wishes to find times for other "implementations". /cliff | |||||