Conference noted::hackers_v1

The answer to where Mel went is, of course, writing microcode for one of
the big machines (i.e. a Cray, a Nautilus or something)!

Hugh.

Mel was indispensable in getting all the wires in a Cray the correct length,
(so signals always arrive at the correct time), but did no micro-coding at CRL;
the Cray has no microcode.

	Are you serious?

	KC

Anyone on a PDP-11 ever displayed the two bytes at a CLR (R5)?

Kevin

  Don't tell me some of Richie Lary's code is still in RSTS!  I inherited a
  piece of code, originally written by him, in my first job at DEC.  In it
  was a sequence to print a '<CR><LF>'.  He used R5 to fill the XRB.  One of
  the instructions was 'CLR (R5)' and he used the instruction as the two 
  characters to be written.  Richie's comment in the code (yes, he commented)
  was: "The devil made me do it!"

--Simon

.2 was ABSOLUTELY serious, on both the Cyber series and the Cray's, the wire
length is used to control timing, so the engineers putting the machine together
on site sit there with their oscilliscopes and cut 1/4" pieces of wire off
until the signals are taking the correct time to get thru.

/Bevin

Oh yea, I remember a story (which, if you are bored, you are perfectly
able to turn off).

I forget who originally told me the story, but there was a Cyber FE
trying to fix a machine.  He has tried all sorts of things, and finally
determined that it was a timing problem.  The solution was to take a piece
of wire and wrap it the long way around the machine.

Software is a piece of cake compared to that.

	KC

 While all you old-timers are reminiscing, I'd like to comment on the
poem: it's the usual "boy, programmers today don't know how to code!
Look at the good old days!"  It sounds like a bunch of old pilots on a
modern shuttle flight talking about how great the DC-3's were--want to
fly around in those from city to city?  I look for a different form of
adventure. 

 However, that poem is one of the most elegant descriptions of what it 

If I remember Ritchie's buffer copy code correctly, it ended with
the sequence

	MOV (PC),(R5)+
	CLR (R5)

Note that, to get this right, Ritchie had to make sure the buffer
would be aligned correctly.

When I first joined Dec, I tried modifying the OS8 DECtape driver
to allow reading PDP-11 dectapes (with 512 byte blocks).  Unfortunately
the OS8 DECtape format used 128 byte blocks and the wordcount was
stored as a 2-s complement number (octal 7200).  Since this was
a perfectly valid PDP-8 machine instruction and since the driver
just fit into 128 words, etc. etc.  I never was able to add that
one word of code.

The first operating system for the PDP-11, Dos used to stuff the
next instruction into a device register:

	MOV (PC),@#177564
	RTS PC

The 207 value of RTS PC would set interrupt enable and GO.  When the
DL-11 arrived, one of the loworder bits was used to control break
generation and we had a merry time cutting jumper J5 to get our
machines working again.

Ahh memories.

How about the following instruction placed in loc 157776
and executed?

MOV -(PC),-(PC)


or the following executed from 000000 on an 11/40 with R0, R6 = 0

000002	CLR (0)+
000004	BR-(2)		Code 776 (I forget my mnemonics)


Anyone know what will happen?

We used these a lot when I was a tech, to check basic memory integrity.


Mike

The fastest code on an 11/45 was executed in the memory management registers !

Does anyone know how the MM registers in the 11/70 compare with cache ?

                                                                       -PeterM-

The 11/05 and 11/10 CPUs allowed code in the general registers -

	1st inst in R0
	2nd inst in R2
	3rd      in R4
	4th      in R6

Use R1, R3, and R5 as scratch registers.

Branch instructions behave peculiarly.

                                                                       -PeterM-

On the PDP-10 the registers were simply the first 16 words of
memory. (There was even a switch to enable/disable high speed
memory for them on the front panel.) You could load instructions
into them and JUMP or CALL to location 0. 

This was used so often that the assembler had special opcodes to
indicate that code would be relocated to another place before it
was executed: 

	PHASE 0
loop:	...
	JUMPL	loop
	RETURN
	DEPHASE

You had to load it into the registers yourself, then all you had
to do was:

	CALL 0

Andy V

Re .11:

The first one was a real legend in college (MOV (PC)-,(PC)-).  It was
known by the octal for it, rather than the name.  Too bad I forgot it.

Re .14:

Unfortunately, the ACs were slower than cache by the KL, and so programs
that do this (and you can tell with ^T) aren't so optimal any more.

(It's much easier to JRST into the ACs than to JUMP to them; it's difficult
to JUMP anywhere).
				/AHM

re .15:  Yes, I know that JRST is faster, but people who
don't know the PDP-10 instruction set would be confused. 

For those who care, JRST = "Jump and ReSeT flags", and a
plain JUMP is "JUMP never". If you really want to jump, you
must say JUMPA for "JUMP Always" or JUMPL for "JUMP
Lessthan" or ... 

Andy V

Re .15 continued: 

Also, there is no CALL -- you normally used "PUSHJ P,addr"
to call a routine and a "POPJ P," to return.  There are a
couple of other ways to call routines, but I don't remember
them off-hand. 

I am suprised to hear that the KL10 cache is faster than the
registers. I used a KA10 that ran for a long time on DECtape
before we got a disk drive. 

Andy V

Just ragging on you.

Actually, JRST means "Jump and ReSTore".  In the usual case, "JRST 0,ea",
nothing gets restored, but there are 15 other cases, with several
interpretations depending on the processor type and current mode.

Other subroutine call instructions include:

PUSHJ	PUSH and Jump
JSR	Jump to SubRoutine
JSP	Jump and Save Pc
JSA	Jump and Save Ac
XCT	eXeCuTe
UUO	Unimplemented User Operation

There's also a couple of return instructions

POPJ	POP and Jump
JRSTF	Jump and ReSTore Flags
JRA	Jump and Restore Ac

JSA/JRA are about the most complex and losing.
				/AHM

The MOV -(PC),-(PC) is 14747 (known via some sig newsletters as
the '47 test')

Here's another one for you:

	0/	15740
	15740/	0
	r0/	160000
	0G

on an LSI.

Try it, you'll like it...

I'd love to see that on the address lights of an 11/40 or 11/70!


-Mike-

Now there was a test of a programmer...

To get the address and data lights running in all sorts of fancy patterns 
on RSTS or RSX (but then with supervisor mode, it was easy...)

Give us good NUL jobs and plenty of lights to play with...

John

The IBM 1401 computer controlled the 1403 printer directly, as I recall, with
no hardware buffering.  The strike of each hammer in the printline was under
program control.

In 1965 I watched and listened in horror-struck awe as a program ran on the
1401 in UC Berkeley's Computer Center that caused the 1403 to HUM the theme
from "The Bridge Over the River Kwai" and several other melodies.  It was
done by controlling the timing of how the 132 hammers struck the paper, and
the rhythm was the little "click" of the paper advancing a line.

Whoever wrote that was a R.P.

---Pete

I had a null job for RTS-8 (on a PDP-12) that played the
Star War's theme music.  The PDP-12 came with a built-in
speaker that was driven off the pulsing of AC bit 0.

The same computer room (cf .-2) held an IBM 7040 and an IBM 7094.  One program
for the 7094 produced music by using an AM radio with an antenna that was just
a wire, wrapped around the L light on the console.  Flickering the light on and
off generated the sound.  This wasn't easy, since the L light didn't have to do
with the usual programmable register settings.

The 7094 also had a bank of lights 15 wide by 7 deep that showed the contents
of the index registers.  I wrote a program to make these be a moving message
display.

And finally, in the same installation (and later in many other installations) I
heard a program make "music" on the 1401 by playing through an AM radio simply
placed atop the CPU.  With FCC compliance, those days are gone.

---Pete

The 1401 example wasn't quite as stated in a previous response.
You controlled the 1403 printer by loading a line in the print
buffer and executing the "print" instruction.  Time and bad
living have purged the exact mnemonic from my working storage.

The printer contained a chain of type and logic to hit the hammer
when the proper character was in the proper position.  By spacing
the characters properly, you can get different tones:

	E    E    E    E ...
	E         E        E

The second line should give a lower-pitched noise.  "Music" consisted
of a deck of cards, appropriately punched, and a card-to-printer
listing program.

In addition to music, there was at least one card deck which was
punched in such a way as to cause the chain to resonate, and eventually
break.

Loudspeakers attached to computer logic dates back well into the '50s.
We used them as diagnostic tools, as well as to play music.

Martin.

Before I worked for DEC, I had some friends in WS (West Springfield)
where the tape drives get their burn-in.  Some of the diagnostics people there
had set up the burn-in programs for the TU-78 so that it would play "Mary
had a little lamb".  The tape spinning forward a few blocks, then back a
couple, and forward some more,..etc, provided the sound.   

Rumor has it you can walk up to any production TU78, type the right 
combination of numbers on the little keypad down below the reels and
have this occur.

Rick

PS.  If you're interested some time, ask them about the tank they made out
     of tape drive motors and takeup reels.  

The Burroughs 6700 had a large rectangular bank of lights that displayed
the Burroughs logo (a large capital B) as the idle pattern.  I used the
B6700 at the US Air Force Academy, and of course, some unknown real programmer
had changed the idle pattern to display AF.

Figures....


My favorite type of system console is the one on the CDC 6000 series.
It's a pair of 18-inch or so round scopes, with two display modes:
dot graphics (one dot per microsecond) or vector-stroke characters
(one per microsecond or so, three sizes).  The display control is
connected directly to the I/O channel, and driven by a dedicated
peripheral processor.  By default you got the system status (sort of
like WHAT or VT5DPY or whatever -- except that it's in real time
since the screen is updated 50 times per second directly from the
system tables).  But you could run all sorts of games on it to
while away the time at late night shifts.  One good example was
the kaleidoscope -- great in combination with certain controlled
substances.

Another handy one is the PC watcher: it uses the "read PC" instruction,
breaks down the 18-bit result into 9-bit X and 9-bit Y, and plots
a dot there.  Great way to find the "hot spots".

Finally, there was "lunar lander".  Not the easy one like on the GT40,
but one like a true flight simulator -- with a view from the pilot's
station out the windows and on the controls.  I never got past the
point of seeing stars and craters spinning past the window lik
crazy... 

	Paul

...and speaking of hacking machine code:

The 6000 series machines have a bootstrap which consists of a panel
of 12 rows of 12 switches, i.e. a 12-word program to be executed by
a PPU.  (why 12 words?  For symmetry, of course!)

It's always fun to try to cram anything in 12 words, but the best
challenge was to use the first 5 words or so to transfer the next 7
to another PPU, which would then execute the next 5 to read the
secondary boot off the disk and use the last 2 words as parameter
to be passed to the secondary boot...

Way back in the dim days when PDP11/70s were something new, a student on a
hardware course in READING, ENGLAND happenned on a program which would blow
the fuse on the TU10 tape drive.  A little bit of forgetting to check the
ready bit and woops went the fuse driving the reel motor power supply.

PeterM

The field image copy of DDT for the -20 depends upon the fact that the
instruction SETA (opcode 424) is both a no-op and a legal indirect word.
				/AHM
P. S.  What does the number of no-ops in an architecture have to do with RISC?

RE: -1

  I think what he meant was:

RISC = Reduced Instruction Set Computer.

PDP-10 has millions of NO-OPs. Therefore, a machine with only one NO-OP
is a RISC. Right ?

trev

The PDP-11 has "0", zero, zilch NOP instructions.  How's that for RISC.

The 240 instruction commonly referred to as NOP is actually a
"Clear no Cond codes" instruction.  Similarly the 260 instruction is actually
"Set no Cond codes".  Also any of the branch instructions (seventeen) with an
offset of zero should NOP.

PAL-11-A (remember those days) barfed on the NOP mnemonic.

Come to think of it, PAL-11-A didn't understand PDP-11 registers ! ! !

PeterM

Re .33

    Right.

    Reducing the number of useful instructions only impacts dull, serious
    programmers.  Hackers only become concerned when the number of NOP's
    is reduced.

Re .34

    I believe you misunderstand.  ANY instruction that does nothing but
    waste time is a NOP.  Clear nothing is a NOP.  Set Nothing is a NOP.
    Branch Never is a NOP.  I don't know how many NOP's there are in the
    PDP-11 instruction set, but there certainly are some.  It makes no
    difference whether an op-code is reserved for NOP.  In fact, reserving
    an OPCODE for NOP is bad engineering of the OPCODE space.

Ah, but the word Reduced refers to the power and complexity of instructions,
not the number of different instructions.

Re .-1:

There are at least two uses for a NOP instruction.  One is to waste time, and
one is to waste space.  I have never used a NOP to waste time in a program,
but I have often used a NOP to fill up space after things like a subroutine
call with skip returns.  It is a matter of interest as to which NOP is the
fastest in such circumstances.

(Actually I suppose putting NOPs in the non-skip slot after a routine call
would be more like alignment than wasting space.  Putting them in code to
leave space for patching would be a space wasting application).
				/AHM

Re:	240 (the standard PDP11 NOP)

It is also a space character with the high-bit (sometimes) 
parity set. Anyone used it as such??

My point was that the NOP instruction does not exist in the PDP-11
architecture - WHAT ! who said architecture ?

The NOP assembler mnemonic was added as an afterthought and was implemented
as a clear no cond-codes.

Maybe it was fashionable to implement NOPs in computers in those days.

Suggestion

	Real computers have the NOP instruction implemented in
	microcode or in logic !

PeterM

Ah, yes.  This discussion brings back such memories...

I've used NOPs (on PDP-11s) as a time-waste.

A PDP-11/20 of bygone days had a floating point unit which was accessed by
some 'memory' registers.  Since the floating-point operations were pretty
fast (relative to the 11), and checking for completion of the floating-point
operation rather tedious (and sometimes caused a few unused micro-seconds of
CPU time), and the timings of both the PDP-11/20 instructions and the floating-
point unit were clearly stated, it was 'better' to just generate a few 'nop'
instructions to wait the requisite amount of time.

This was done by a macro (of course), which sometimes generated a few nops
(of various flavors), sometimes a little loop, ..., all meticulously timed.

Re .37: I've see a non-standard NOP used to SAVE space...

Some background:

	- The RT11 exec is position-independent code
	- The RT11 .PRINT system service (EMT) takes the address of
	  the string to print in R0
	- If the string is terminated by a null (.ASCIZ), the .PRINT
	  adds a CR LF to it

So therefore, when the CLI code wanted to do a CRLF in position independent
code, the sequence of instructions came out as:

	MOV	PC,R0
	MOV	R0,R0		;NOP whose low byte is zero!
	.PRINT

I trust further explanations are superfluous...

	Paul

re:  NOP's and RISC's

Interestingly, every RISC design I've seen includes an explicit NOP - it has to!
You see, one of the design goals of RISC architectures is that EVERY instruction
take one cycle time.  This causes a problem for conditional branches:  You need
to do two things in sequence - test the condition - even if it's a single bit -
and then either change or not change the PC.  Just the load of the PC will
take as long as, say, loading a register - so you'd need to lengthen the cycle
time - slowing down the whole machine - just to accomodate the conditional
branches.  Further, a big advantage of the fixed size/fixed cycle time instruc-
tions is that they can easily be pipelined.  However, when a branch is taken
(conditional or not) the next instruction in the pipe becomes invalid, which
costs you a cycle.

The solution, adopted from long micro-programming practice, is the so-called
"delayed branch".  This is a branch that doesn't "take" until one cycle
AFTER it is issued.  Thus, if DBR were a delayed branch:

	1:	MOV	#0,A
	2:	DBR	FOO
	3:	MOV	#0,B
	4:
	...
	FOO:	xxx

The instructions are executed in the order (1), (2), (3), (FOO).

In most cases - typically 90% or more in compiler-generated code - the in-
struction just before the DBR can safely be moved after the DBR.  Then the
code gets executed at the maximum rate possible.  There are always the
remaining cases - things like successive branches, for example - that can't
be interchanged.  In that case, you need a NOP to put after the DBR.

(Another alternative, of course, is to have both BR's and DBR's.  Most RISC's
don't do this since they usually have room in the instruction word to include
a register or two, so they tend to have a bunch of branches - BR if 0, if >0,
etc. - rather than variations on one branch; so they'd need to duplicate a
variety of branches, rather than introducing one NOP, which will only very
rarely be used anyway.  (It will also save space, but not time - the delay
for a non-delayed branch will still have to be there.))

							-- Jerry

BTW, for missing instructions:  The VAX appears to be the first significant
architecture without an explicit WAIT (for interrupt) instruction.	-- J

Re .41: what you describe as "RISC" sounds more like a typical 2901-based
microcontroller.  For example the UDA50 microengine works that way.
But I've never seen a general-purpose CPU of the RISC flavor that
has deferred branch.  Nor is it necessary for RISC machines to have
only one-cycle instructions, or fixed-length cycles.

As for the missing WAIT: I rather suspect it's the other way around, with
the PDP11 being one of the few that DOES have one.  For example, the PDP8,
IBM 360, and Cyber 6000 all get along without it.

	Paul

Old PDP-11 Dos-11 hackers will fondly recall that the 11/20
had two wait-for-interrupt instructions.  The guts of that
marvelous o.s. used
	BR	.
to wait for an interrupt.

Anyone remember why?

	[RE .43]:  Well, Martin; are you going to keep us in suspense any
longer?
#6	<_Jym_>\

Well, Lou Cohen actually wrote that code.  He has now repented
of his evil past and is working on improving software quality.

If I remember the history correctly, on the 11/20, if there
was an interrupt pending when you executed the WAIT, the cpu
waited anyway (until the NEXT interrupt request).  BR .
just spun around until something happened.  Rumor has
it that the same bug was in the 11/34, too.

Martin.

In my old TOPS-10 days we had a contest to see who could write the smallest
program that did a printed a directory on your terminal.  I can't remember
who won, but it it was the guy who used an

	INBUF 5,

which is an ASCIZ CR, LF.  (INBUF makes buffers from free memory for I/O).

Another guy used a 

	POPJ P,'UFD'

preceeded by a SKIPA instruction with the AC field non-zero (because
SKIPA 1,ADDR loads AC with contents of ADDR and skips always, and the
location before the POPJ was used for your PPN to look up your UFD).

GAS