[Search for users] [Overall Top Noters] [List of all Conferences]

Conference ecadsr::verilog_vhdl

Title:	verilog

Moderator:	ECAD2::KINZELMAN

Created:	Tue Mar 31 1992
Last Modified:	Wed Oct 12 1994
Last Successful Update:	Fri Jun 06 1997
Number of topics:	21
Total number of notes:	42
Number with bodies:	0

a * after the topic number in the table indicates the body of the base post is in the cache and a + after the topic number indicates at least one replies body is in the cache (*+ means both are true)

Click here for list of top noters for this conference

Topic
# Replies Author Written Subject
1.0 1 ECAD2::KINZELMAN Tue Mar 31 1992 Welcome to the VERILOG-XL and VHDL-XL conference
2.0 PLOUGH::KINZELMAN Tue Mar 31 1992 Cadence release information
3.0 FIONN::COFFEY Thu Apr 02 1992 VHDL-XL vs Synopsys
4.0 MAST::RUPP Fri Apr 03 1992 Verilog TURBOchannel Models
5.0 PLOUGH::KINZELMAN Fri May 15 1992 Verilog mixed mode performance problems?
6.0 1 JANUS::GALUSZKA Thu May 21 1992 VHDL-XL : impressions following a demonstration
7.0 YIELD::KAU Fri May 22 1992 DEC-VERILOG on PC ?
8.0 2 NUPE::hamp Wed Jun 17 1992 Memory allocation problem?
9.0 1 MAST::OLIVEIRA Wed Jul 15 1992 CUPL -> Verilog behavioral converter
10.0 PLOUGH::KINZELMAN Tue Jul 28 1992 QUAD Design tools conference
11.0 MARVIN::HAQUE Mon Aug 10 1992 Do you need gSTATE in the future?
12.0 NUPE::hamp Thu Sep 03 1992 DECSIM to VERILOG?
13.0 5 UGETIT::ELDRIDGE Mon Nov 02 1992 System Simulation using VHDL
14.0 3 ECADSR::BIRO Wed Feb 10 1993 VeriWell Verilog-XL PC CLONE
15.0 3 ISEQ::COFFEY Thu Feb 11 1993 Synopsys notes file?
16.0 2 TRLIAN::NSG Mon Apr 26 1993 Verilog to VHDL anyone???
17.0 GMCTRK::FERREIRA Thu Jun 03 1993 WANTED: Verilog and Composer Licenses
18.0 2 ECADSR::HAMPTON Thu Jun 17 1993 EDA Data Engineering Services
19.0 MARVIN::DOSANJH Fri Jun 18 1993 ** For Sale (LM1
20.0 1 ECADSR::BIRO Mon Apr 11 1994 VIUF Spring 94
21.0 RICKS::WASSON Wed Oct 12 1994 verilog -> C translator

Topic #	Replies	Author	Written	Subject
1.0	1	ECAD2::KINZELMAN	Tue Mar 31 1992	Welcome to the VERILOG-XL and VHDL-XL conference
2.0		PLOUGH::KINZELMAN	Tue Mar 31 1992	Cadence release information
3.0		FIONN::COFFEY	Thu Apr 02 1992	VHDL-XL vs Synopsys
4.0		MAST::RUPP	Fri Apr 03 1992	Verilog TURBOchannel Models
5.0		PLOUGH::KINZELMAN	Fri May 15 1992	Verilog mixed mode performance problems?
6.0	1	JANUS::GALUSZKA	Thu May 21 1992	VHDL-XL : impressions following a demonstration
7.0		YIELD::KAU	Fri May 22 1992	DEC-VERILOG on PC ?
8.0	2	NUPE::hamp	Wed Jun 17 1992	Memory allocation problem?
9.0	1	MAST::OLIVEIRA	Wed Jul 15 1992	CUPL -> Verilog behavioral converter
10.0		PLOUGH::KINZELMAN	Tue Jul 28 1992	QUAD Design tools conference
11.0		MARVIN::HAQUE	Mon Aug 10 1992	Do you need gSTATE in the future?
12.0		NUPE::hamp	Thu Sep 03 1992	DECSIM to VERILOG?
13.0	5	UGETIT::ELDRIDGE	Mon Nov 02 1992	System Simulation using VHDL
14.0	3	ECADSR::BIRO	Wed Feb 10 1993	VeriWell Verilog-XL PC CLONE
15.0	3	ISEQ::COFFEY	Thu Feb 11 1993	Synopsys notes file?
16.0	2	TRLIAN::NSG	Mon Apr 26 1993	Verilog to VHDL anyone???
17.0		GMCTRK::FERREIRA	Thu Jun 03 1993	WANTED: Verilog and Composer Licenses
18.0	2	ECADSR::HAMPTON	Thu Jun 17 1993	EDA Data Engineering Services
19.0		MARVIN::DOSANJH	Fri Jun 18 1993	** For Sale (LM1
20.0	1	ECADSR::BIRO	Mon Apr 11 1994	VIUF Spring 94
21.0		RICKS::WASSON	Wed Oct 12 1994	verilog -> C translator