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Conference ecadsr::verilog_vhdl

Created:Tue Mar 31 1992
Last Modified:Wed Oct 12 1994
Last Successful Update:Fri Jun 06 1997
Number of topics:21
Total number of notes:42
Number with bodies:0
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1.01ECAD2::KINZELMANTue Mar 31 1992Welcome to the VERILOG-XL and VHDL-XL conference
2.0PLOUGH::KINZELMANTue Mar 31 1992Cadence release information
3.0FIONN::COFFEYThu Apr 02 1992VHDL-XL vs Synopsys
4.0MAST::RUPPFri Apr 03 1992Verilog TURBOchannel Models
5.0PLOUGH::KINZELMANFri May 15 1992Verilog mixed mode performance problems?
6.01JANUS::GALUSZKAThu May 21 1992VHDL-XL : impressions following a demonstration
7.0YIELD::KAUFri May 22 1992DEC-VERILOG on PC ?
8.02NUPE::hampWed Jun 17 1992Memory allocation problem?
9.01MAST::OLIVEIRAWed Jul 15 1992CUPL -> Verilog behavioral converter
10.0PLOUGH::KINZELMANTue Jul 28 1992QUAD Design tools conference
11.0MARVIN::HAQUEMon Aug 10 1992Do you need gSTATE in the future?
12.0NUPE::hampThu Sep 03 1992DECSIM to VERILOG?
13.05UGETIT::ELDRIDGEMon Nov 02 1992System Simulation using VHDL
14.03ECADSR::BIROWed Feb 10 1993VeriWell Verilog-XL PC CLONE
15.03ISEQ::COFFEYThu Feb 11 1993Synopsys notes file?
16.02TRLIAN::NSGMon Apr 26 1993Verilog to VHDL anyone???
17.0GMCTRK::FERREIRAThu Jun 03 1993WANTED: Verilog and Composer Licenses
18.02ECADSR::HAMPTONThu Jun 17 1993EDA Data Engineering Services
19.0MARVIN::DOSANJHFri Jun 18 1993** For Sale (LM1
20.01ECADSR::BIROMon Apr 11 1994VIUF Spring 94
21.0RICKS::WASSONWed Oct 12 1994verilog -> C translator